CADSTAR 16                                   ±â¼úÀÚ·á                                    2015-09-14

 

 


PCB µðÀÚÀλóÀÇ Error °Ë»çÇϱâ

 


Assignments¿¡¼­ Á¤ÀÇÇÑ µðÀÚÀÎ ¼³°è±ÔÁ¤À» ±âÁØÀ¸·Î ÇÏ¿© PCB µðÀÚÀλóÀÇ ¾î´À °÷¿¡¼­ Error°¡ ¹ß»ýµÇ¾ú´ÂÁö¸¦ Check ÇÑ´Ù.

¿©±â¿¡´Â µÎ °¡ÁöÀÇ ¼³°è±ÔÁ¤ ±×·ìÀ» °¡Áö°í ÀÖ´Ù.

         
Spacing
        Manufacturing

1.          Spacing °ú Manufacturing Error Codes
            

             (S) = Spacing Rule       (M) = Manufacturing Rule

AC Height Clearance (S)

IR Incomplete Routing (S)

AK   Area Keepout (S)

PB   Pad to Board Outline (S)

AV   Area No Vias (S)

PC   Pad to Copper (S)

AA   Comp Placement to Comp Placement (S)

PP   Pad to Pad (S)

BC   Comp Copper to Board Outline (S)

RO   Route Offset (M)

BD   Teardrop to Board Outline (S)

SS   Width Change Seg Too Short (M)

BT   Text to Board Outline (S)

TB   Route to Board Outline (S)

CB   Copper to Board Outline (S)

TC   Route to Copper (S)

CM   Comp Copper to Comp Copper (S)

TP   Route to Pad (S)

CO   Comp Copper to Copper (S)

TT   Route to Route (S)

CP   Comp Copper to Pad (S)

TV   Route to Via (S)

CR   Comp Copper to Route (S)

TS   Thin Route Segment (M)

CV   Comp Copper to Via (S)

TK   Area No Routes (S)

CC   Copper to Copper (S)

VB   Via to Board Outline (S)

CH   Copper Hatching Isolation (M)

VP   Via to Pad (S)

DD   Drill Holes Too Close (M)

VC   Via to Copper (S)

EC   Teardrop to Comp Copper (S)

VV   Via to Via (S)

EO   Teardrop to Copper (S)

XC   Text to Comp Copper (S)

EP   Teardrop to Pad (S)

XO   Text to Copper (S)

EE   Teardrop to Teardrop (S)

XP   Text to Pad (S)

ET   Teardrop to Text (S)

XV   Text  to Via (S)

ER   Teardrop to Route (S)

XR   Text to Route (S)

EV   Teardrop to Via (S)

XX   Text to Text (S)

IC   Isolated Copper (M)

 

 

2.          Report ¸Þ´º ÅÇÀÇ Design Rule Check¸¦ ¼±ÅÃÇÑ´Ù.

             


2.1         Type of Check

All - À§¿¡¼­ ¾ð±ÞµÈ Spacing°ú ManufacturingÀÇ ¸ðµç Ç׸ñÀ»

°Ë»çÇÑ´Ù.

Spacing Only - À§¿¡¼­ ¾ð±ÞµÈ Spacing¿¡ ¾ð±ÞµÈ Ç׸ñ(±×

Ç׸ñ»çÀÌÀÇ °£°ÝÀÌ Àû´çÇÑÁö)À» °Ë»çÇÑ´Ù.

Manufacturing Only - À§¿¡¼­ ¾ð±ÞµÈ Manufacturing¿¡ ¾ð±ÞµÈ

Ç׸ñÀ» °Ë»çÇÑ´Ù.

Selected - À§¿¡¼­ ¾ð±ÞµÈ Ç׸ñ Áß ¿øÇÏ´Â ³»¿ë¸¸ °ñ¶ó¼­ °Ë»çÇÑ´Ù.

Choose ¹öÆ°°ú °°ÀÌ »ç¿ëµÈ´Ù.

 

Choose ¹öÆ°À» ¼±ÅÃÇÏ¸é ´ÙÀ½ÀÇ Ã¢ÀÌ ³ªÅ¸³­´Ù.

 

 

À§ÀÇ Ã¢À» º¸¸é µÎ ¿µ¿ªÀ¸·Î ºÐ¸®µÇ¾î ÀÖ´Â °ÍÀ» º¼ ¼ö ÀÖ´Ù.

 

Rules Included : ÀÌ ¿µ¿ªÀÇ ¸ñ·Ï¿¡ ³ªÅ¸³­ Ç׸ñ¸¸ °Ë»çÇÑ´Ù.

 

All - À§¿¡¼­ ¾ð±ÞµÈ Manufacturing °ú Spacing ±ÔÁ¤ÀÇ ¸ðµç Ç׸ñÀÌ ¿ÞÂÊ »ó´ÜÀÇ Included ¿µ¿ª¿¡ Ãß°¡µÈ´Ù. ÀÌ°ÍÀ» ¼±ÅÃÇÏ¸é ¿À¸¥ÂÊ »ó´ÜÀÇ Excluded ÆгÎÀº ºóÄ­ÀÌ µÈ´Ù.


Spacing -
À§¿¡¼­ ¾ð±ÞµÈ Spacing ±ÔÁ¤ÀÇ ¸ðµç Ç׸ñÀÌ ¿ÞÂÊ »ó´ÜÀÇ Included ¿µ¿ª¿¡ Ãß°¡µÈ´Ù.


Manufacturing -
À§¿¡¼­ ¾ð±ÞµÈ Manufacturing ±ÔÁ¤ÀÇ ¸ðµç Ç׸ñÀÌ ¿ÞÂÊ »ó´ÜÀÇ Included ¿µ¿ª¿¡ Ãß°¡µÈ´Ù.

Included ¿µ¿ªÀÇ ¸ñ·Ï Áß ¿øÇÏÁö ¾Ê´Â Ç׸ñÀ» Á¦¿ÜÇÏ°íÀÚ ÇÒ ¶§´Â Ç׸ñÀ» ´õºíŬ¸¯ ÇÑ´Ù. ´õºíŬ¸¯ ÇÑ Ç׸ñÀÌ ¿À¸¥ÂÊ Excluded ¿µ¿ªÀ¸·Î À̵¿µÈ´Ù.

 

 

Rules Excluded : ÀÌ ¿µ¿ªÀÇ ¸ñ·ÏÀº °Ë»ç´ë»ó¿¡¼­ Á¦¿ÜÇÑ´Ù.

 

All - À§¿¡¼­ ¾ð±ÞµÈ Manufacturing°ú Spacing ±ÔÁ¤ÀÇ ¸ðµç Ç׸ñÀÌ ¿À¸¥ÂÊ »ó´ÜÀÇ Excluded ¿µ¿ª¿¡ Ãß°¡µÈ´Ù. ÀÌ°ÍÀ» ¼±ÅÃÇÏ¸é ¿ÞÂÊ »ó´ÜÀÇ Included ÆгÎÀº ºóÄ­ÀÌ µÈ´Ù.


Spacing -
À§¿¡¼­ ¾ð±ÞµÈ Spacing ±ÔÁ¤ÀÇ ¸ðµç Ç׸ñÀÌ ¿À¸¥ÂÊ »ó´ÜÀÇ Excluded ¿µ¿ª¿¡ Ãß°¡µÈ´Ù.


Manufacturing -
À§¿¡¼­ ¾ð±ÞµÈ Manufacturing ±ÔÁ¤ÀÇ ¸ðµç Ç׸ñÀÌ ¿À¸¥ÂÊ »ó´ÜÀÇ Excluded ¿µ¿ª¿¡ Ãß°¡µÈ´Ù.

Excluded ¿µ¿ªÀÇ ¸ñ·Ï Áß °Ë»çÇϱ⠿øÇÏ´Â Ç׸ñÀ¸·Î Æ÷ÇÔÇÏ°íÀÚ ÇÒ ¶§´Â Ç׸ñÀ» ´õºíŬ¸¯ ÇÑ´Ù. ´õºíŬ¸¯ ÇÑ Ç׸ñÀÌ ¿ÞÂÊ Included ¿µ¿ªÀ¸·Î À̵¿µÈ´Ù.

 

 

2.2         Layers to Check

 

All - µðÀÚÀο¡ ¼³Á¤µÈ ¸ðµç Electrical Layer¸¦ °Ë»çÇÑ´Ù.

Single  µðÀÚÀο¡ ¼³Á¤µÈ Electrical LayerÁß Çϳª¸¸À» °ñ¶ó¼­ °Ë»çÇÑ´Ù.

Selected - µðÀÚÀο¡ ¼³Á¤µÈ Electrical Layer Áß ¿øÇÏ´Â Layer¸¸ °ñ¶ó

°Ë»çÇÑ´ÙChoose ¹öÆ°°ú °°ÀÌ »ç¿ëµÈ´Ù.

 

             Choose ¹öÆ°À» ¼±ÅÃÇÏ¸é ´ÙÀ½ÀÇ ´ÙÀ̾˷αװ¡ ³ªÅ¸³­´Ù.

 

            

À§ÀÇ ´ÙÀ̾˷α׸¦ º¸¸é µÎ ¿µ¿ªÀ¸·Î ºÐ¸®µÇ¾î ÀÖ´Â °ÍÀ» º¼ ¼ö ÀÖ´Ù.

Layers Included :
ÀÌ ¿µ¿ªÀÇ ¸ñ·Ï¿¡ ³ªÅ¸³­ Layer¸¦ °Ë»çÇÑ´Ù.

 

Included ÆгÎÀÇ ¸ñ·Ï Áß ¿øÇÏÁö ¾Ê´Â layer¸¦ Á¦¿ÜÇÏ°íÀÚ ÇÒ ¶§´Â Ç׸ñÀ» ¼±ÅÃÇÏ°í ´õºíŬ¸¯ ÇÑ´Ù. ´õºíŬ¸¯ ÇÑ Ç׸ñÀÌ ¿À¸¥ÂÊ Excluded ¿µ¿ªÀ¸·Î À̵¿µÈ´Ù.

 

Layers Excluded : ÀÌ ¿µ¿ªÀÇ ¸ñ·Ï¿¡ ³ªÅ¸³­ layer¸¦ °Ë»ç´ë»ó¿¡¼­ Á¦¿ÜÇÑ´Ù.

Excluded ¿µ¿ªÀÇ ¸ñ·Ï Áß °Ë»çÇϱ⠿øÇÏ´Â Layer¸¦ Æ÷ÇÔÇÏ°íÀÚ ÇÒ ¶§´Â Ç׸ñÀ» ¼±ÅÃÇÏ°í ´õºíŬ¸¯ ÇÑ´Ù. ´õºíŬ¸¯ ÇÑ Ç׸ñÀÌ ¿ÞÂÊ Included ¿µ¿ªÀ¸·Î À̵¿µÈ´Ù.

 

             2.3         Where to Check

 

            

Whole Design - Board Outline¾ÈÀÇ ¸ðµç Ç׸ñÀ» °Ë»çÇÑ´Ù

In Current Window  ÇöÀç È­¸é¿¡ ³ªÅ¸³­ ºÎºÐ¸¸À» °Ë»çÇÑ´Ù.

In Area - »ç¿ëÀÚ°¡ ¿øÇÏ´Â ºÎºÐ¸¸À» °ñ¶ó °Ë»çÇÑ´Ù.

 

             2.4         °Ë»ç½ÃÀÛÇϱâ

À§ÀÇ ³»¿ëÀ» ÂüÁ¶ÇÏ¿© °Ë»çÇÏ°íÀÚ ÇÏ´Â ³»¿ëÀ» ÁöÁ¤ÇÏ°í ´ÙÀÌ¾Ë·Î±× ¿ÞÂÊ ÇϴܺÎÀÇ Begin Check ¹öÆ°

()À» ´©¸£¸é °Ë»ç¸¦ ½ÃÀÛÇÑ´Ù.

 

°Ë»ç°¡ ¿Ï·á µÇ¸é È­³ä ¾Æ·¡ ºÎºÐ¿¡ Design Rule Error Reports°¡ ÀÚµ¿À¸·Î ¿Ã¶ó¿À¸ç µðÀÚÀÎ ¿µ¿ª¿¡´Â Error°¡

¹ß»ýÇÑ ºÎºÐ¿¡ Error Code°¡ ³ªÅ¸³­´Ù.

 



ÀÌ ±â¼úÀÚ·á ³»¿ë¿¡ °üÇÑ ¹®ÀÇ»çÇ×ÀÌ ÀÖÀ¸½Ã¸é ¾Æ·¡·Î ¿¬¶ô Áֽñ⠹ٶø´Ï´Ù.


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